A familiar dynamic circuit arrangement in CMOS IC chips comprises an arrangement where the output of one dynamic stage drives directly the next consecutive dynamic stage without inversion of signals therebetween. To drive such directly coupled dynamic circuits at high frequency, first and second clock signals are used. The second clock signals lag the first clock signals by an appropriate phase angle. The first and second clock signals are connected to all the first stages and to all the second stages, respectively, to enable the first and second stages with appropriate time delay. The second stage dynamic gates are enabled by the second clock signals only after the first stage gates have produced stable outputs. To produce the desired precisely delayed second clock signals from a single clock source using complementary MOS (CMOS) circuitry is one of the most difficult design problems. This is because of the inability to control precisely certain variables in the fabrication process that affect pullup and pulldown delays in the fabricated chips. Channel length of a MOS field-effect transistor is an example of such variables. Since N-channel MOSFETs and P-channel MOSFETs use arsenic and boron diffusion to fabricate the drain/source areas, respectively, and since their diffusion coefficients are different, the channel lengths of an NFET and a PFET vary independently of each other. These channel length variations generate uncertainties in pullup and pulldown delay times. Thus, two separate clock circuits are typically used in a PLA (programmable logic array)-like dynamic logic circuit; alternatively, static CMOS logic circuits are used, which require no clock signal, for slower speed applications. Thus, at the present time, no reliable technique has been developed of generating clock signals for cascaded, high speed dynamic CMOS logic circuits with only one clock input.